1. Field of the Invention
The present invention generally relates to read/write transactions on a computer bus and more particularly, but not by way of limitation, to a method and apparatus for supporting interleaved read/write operations for multiple target devices in a multicast computer environment.
2. Description of the Related Art
A conventional computer system typically includes one or more Central Processing Units (CPUs) capable of executing algorithms forming applications in a computer main memory. Peripheral devices, both those embedded together with a CPU or constructed to be separate therefrom, also typically form portions of a conventional computer system. Computer peripheral devices include, for instance, video graphics adapters, Local Area Network (LAN) interfaces, Small Computer System Interface (SCSI) bus adapters, and mass storage devices, such as disk drive assemblies.
A computer system further typically includes computer buses which permit communication of data between various portions of the computer system. For example, a host bus, a memory bus, at least one high-speed bus, a local peripheral expansion bus, and one or more additional peripheral buses form portions of a typical computer system.
A peripheral bus is formed, for instance, of an SCSI bus, an Extension to Industry Standard Architecture (EISA) bus, an Industry Standard Architecture (ISA) bus, or a Peripheral Component Interface (PCI) bus. The peripheral bus forms a communication path to and from a peripheral device connected thereto. The computer system CPU, or a plurality of CPUs in a multi-processor system, communicates with a computer peripheral device by way of a computer bus, such as one or more of the computer buses noted above.
A computer peripheral, depending upon its data transfer speed requirements, is connected to an appropriate peripheral bus, typically by way of a bus bridge that detects required actions, arbitrates, and translates both data and addresses between the various buses.
Software drivers are typically required for each computer peripheral device to effectuate its operation. A software driver must be specifically tailored to operate in conjunction with the particular operating system operating on the computer. A multiplicity of software drivers might have to be created for a single computer peripheral to ensure that a computer peripheral device is operable together with any of the different operating systems.
The complexity resulting from such a requirement has led, at least in part, to the development of an Intelligent Input/Output (I2O) standard specification. The I2O standard specification sets forth, inter alia, standards for an I/O device driver architecture that is independent of both the specific peripheral device being controlled and the operating system of the computer system to which the device driver is to be installed.
Regardless of which bus protocol is deployed in a computer system or whether the computer system is I2O compliant, devices frequently employ bus master/slave functionality to communicate across a computer system bus. In a typical bus transaction, a single bus master sends information, including, but not limited to, address, data and control information to a single target device operating as a slave during a single bus transaction. In certain situations, however, it is desirable to broadcast the information to multiple targets. For example, in a fault-tolerant environment it is desirable to perform fast backup of data such as by providing mirrored disk drives. Conventional methods for sending information to multiple targets requires moving the information multiple times using multiple bus transactions. Specifically, with respect to I2O compliant systems, this process is particularly inefficient due to well known I2O compliant communication protocol causing significantly longer latencies.
Commonly assigned U.S. Pat. No. 6,230,225 proposes a technique which would effectuate low-latency distribution of data to multiple target devices. It further proposes a technique for multicasting on a computer system bus wherein information from a single bus master is broadcast to multiple targets during a single bus transaction.
Other advances have been made to improve efficiencies for execution of memory bus operations, for example disk striping and partitioned memory. Disk striping is a technique for spreading data over multiple disk drives. The computer system breaks a body of data into units and spreads these units across the available disks. A different approach has been to provide partitioned memory where the data in memory is divided into multiple sections. Partitioned memory results in an entire physical address spacing divided into groups of fixed sizes. Each of partitioned memory is independent from each other such that each partitioned segment is accessed one at a time. Alternatively, the data contained in memory has been arranged in particular ways, such as in a non-contiguous manner, to increase performance. Interleaved memory is a means of accessing memory where the requesting device can access, for example, alternate memory sections or separate data segments immediately, without waiting for memory to catch up (for example, through wait states). Within a partitioned memory, memory devices can be interleaved to improve the memory performance. The processor can access alternate sections immediately. Interleaved memory is one approach for compensating for the relatively slow speed of dynamic RAM (DRAM). Other techniques included page-mode memory and memory caches.